PIC18F4610T-I/ML【PDF 160/234 页】IC MCU FLASH 32KX16 44QFN

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Sheet目录3878

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2009 Microchip Technology Inc.

DS39636D-page 33

PIC18F2X1X/4X1X

2.8

Effects of Power-Managed Modes

on the Various Clock Sources

When PRI_IDLE mode is selected, the designated

primary oscillator continues to run without interruption.

For all other power-managed modes, the oscillator

using the OSC1 pin is disabled. The OSC1 pin (and

OSC2 pin, if used by the oscillator) will stop oscillating.

Secondary

Clock

modes

(SEC_RUN

and

SEC_IDLE), the Timer1 oscillator is operating and

providing the device clock. The Timer1 oscillator may

also run in all power-managed modes if required to

clock Timer1 or Timer3.

In Internal Oscillator modes (RC_RUN and RC_IDLE),

the internal oscillator block provides the device clock

source. The 31 kHz INTRC output can be used directly

to provide the clock and may be enabled to support

various special features, regardless of the power-

managed mode (see Section 22.2 “Watchdog Timer

(WDT)”, Section 22.3 “Two-Speed Start-up” and

Section 22.4 “Fail-Safe Clock Monitor” for more

information on WDT, Fail-Safe Clock Monitor and Two-

Speed Start-up). The INTOSC output at 8 MHz may be

used directly to clock the device or may be divided

down by the postscaler. The INTOSC output is disabled

if the clock is provided directly from the INTRC output.

If the Sleep mode is selected, all clock sources are

stopped. Since all the transistor switching currents

have been stopped, Sleep mode achieves the lowest

current consumption of the device (only leakage

currents).

Enabling any on-chip feature that will operate during

Sleep will increase the current consumed during Sleep.

The INTRC is required to support WDT operation. The

Timer1 oscillator may be operating to support a real-

time clock. Other features may be operating that do not

require a device clock source (i.e., SSP slave, PSP,

INTn pins and others). Peripherals that may add

significant

current

consumption

are

listed

Section 25.2 “DC Characteristics”.

2.9

Power-up Delays

Power-up delays are controlled by two timers, so that

no external Reset circuitry is required for most applica-

tions. The delays ensure that the device is kept in

Reset until the device power supply is stable under nor-

mal circumstances and the primary clock is operating

and stable. For additional information on power-up

delays, see Section 4.5 “Device Reset Timers”.

The first timer is the Power-up Timer (PWRT), which

provides a fixed delay on power-up (parameter 33,

Table 25-10). It is enabled by clearing (= 0) the

PWRTEN Configuration bit.

The second timer is the Oscillator Start-up Timer

(OST), intended to keep the chip in Reset until the

crystal oscillator is stable (LP, XT and HS modes). The

OST does this by counting 1024 oscillator cycles

before allowing the oscillator to clock the device.

When the HSPLL Oscillator mode is selected, the

device is kept in Reset for an additional 2 ms, following

the HS mode OST delay, so the PLL can lock to the

incoming clock frequency.

There is a delay of interval TCSD (parameter 38,

Table 25-10), following POR, while the controller

becomes ready to execute instructions. This delay runs

concurrently with any other delays. This may be the

only delay that occurs when any of the EC, RC or INTIO

modes are used as the primary clock source.

TABLE 2-3:

OSC1 AND OSC2 PIN STATES IN SLEEP MODE

Oscillator Mode

OSC1 Pin

OSC2 Pin

RC, INTIO1

Floating, external resistor should pull high

At logic low (clock/4 output)

RCIO

Floating, external resistor should pull high

Configured as PORTA, bit 6

INTIO2

Configured as PORTA, bit 7

Configured as PORTA, bit 6

ECIO

Floating, pulled by external clock

Configured as PORTA, bit 6

Floating, pulled by external clock

At logic low (clock/4 output)

LP, XT and HS

Feedback inverter disabled at quiescent

voltage level

Feedback inverter disabled at quiescent

voltage level

Note:

See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.

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